In integrated circuits, there is generally a piece of silicon known as a die or chip which contains electrical circuits and which is connected to a lead frame. The chip has bonding pads which are connected to the lead frame by tiny wires. The lead frame has leads which are used for connecting to a printed circuit board as part of a larger system. The leads of the lead frame have a certain amount of inductance as well as capacitance and resistance. There is also some inductance in the wire from the bonding pad to the lead frame. The wire inductance, however, is significantly less than that of the lead frame. The connection of a lead of the lead frame to a circuit board also adds some inductance. As the switching speeds of integrated circuits have increased, this cumulative inductance has begun to have an impact on the performance of the integrated circuit.
Of course it is desirable to have integrated circuits which are very fast. The increased switching speed has also increased the rate at which current changes. This increased rate of current change causes a voltage drop across the inductance. The voltage across an inductance is equal to the inductance times the time rate of change of the current through that inductance. This is expressed as Ldi/dt, where L is the inductance and di/dt is the time rate of change of the current. As the di/dt becomes larger, the voltage across the inductance becomes larger. This voltage drop across an inductance causes a voltage differential between the lead location on the circuit board and the bonding pad to which it is connected on the integrated circuit. This can create a problem of having the internal supply at a different voltage than the voltage of the external supply. This problem can cause the internal supply voltages to differ by so much from their external levels that signals input to the chip are recognized incorrectly.
FIG. 1 shows a conventional output buffer 35 designed to reduce di/dt and a bonding pad 30 to which it couples its output. (See Wang, Karl L., et. al., "A 21-ns 32K.times.8 CMOS Static RAM with a Selectively Pumped p-Well Array," IEEE Journal of Solid-State Circuits, vol. SC-22, no. 5, Oct. 1987.) Output buffer 35 generally comprises a predriver section 10 and an output stage 20. Predriver section 10 comprises a resistor 11, a P-channel transistor 12, an N-channel transistor 13, a resistor 14, a resistor 15, a P-channel transistor 16, an N-channel transistor 17, and a resistor 18. Output stage 20 comprises an N-channel transistor 22, and an N-channel transistor 24.
Resistor 11 has a first terminal connected to a positive power supply voltage terminal V.sub.DD, and a second terminal. Transistor 12 has a source connected to the second terminal of resistor 11, a gate for receiving an input signal D1, and a drain for providing a first predriven signal. Transistor 13 has a drain connected to the drain of transistor 12, a gate for receiving input signal D1, and a source. Resistor 14 has a first terminal connected to the source of transistor 13, and a second terminal connected to a negative power supply voltage terminal V.sub.SS.
Resistor 15 has a first terminal connected to V.sub.DD, and a second terminal. Transistor 16 has a source connected to the second terminal of resistor 15, a gate for receiving a second input signal D2, and a drain for providing a second predriven signal. Transistor 17 has a drain connected to the drain of transistor 16, a gate for receiving D2, and a source. Resistor 18 has a first terminal connected to the source of transistor 17, and a second terminal connected to V.sub.SS.
In output stage 20, an transistor 22 has a drain connected to V.sub.DD, a gate for receiving the first predriven signal, and a source connected to bonding pad 30. Transistor 24 has a drain connected to the source of transistor 22 and to bonding pad 30, a gate for receiving the second predriven signal, and a source connected to V.sub.SS.
In operation, output buffer 35 limits the Ldi/dt voltage drop in the bonding wire, lead frame, and connection to a printed circuit board by using resistors 11, 14, 15, and 18 to limit the di/dt. D1 and D2 are digital signals which assume either a logic high or a logic low. In a typical embodiment when data is to be driven externally, D1 and D2 are complementary and provide a single output data signal, but when no data is to be driven externally, D1 and D2 are both at a high voltage, which places bonding pad 30 in a high impedance state. Another possible embodiment is that D1 and D2 are always complementary signals.
If D1 and D2 are assumed to be complementary, consider a case in which D1 switches from a logic low to a logic high and D2 switches from a logic high to a logic low. When a logic low is present on D1, transistor 12 is conductive and transistor 13 is nonconductive. In a steady-state condition, no current flows through resistor 11 and transistor 12 and the gate of transistor 22 is held at a high voltage. Similarly, when a logic high is present on D2, transistor 16 is nonconductive and transistor 17 is conductive. In the steady-state condition, no current flows through resistor 18 and transistor 17 and the gate of transistor 24 is held at a low voltage. So transistor 22 is conductive and transistor 24 is nonconductive, driving the value on bonding pad 30 to a logic high.
When D1 switches to a logic high and D2 switches to a logic low, the logic high on D1 makes transistor 12 nonconductive and transistor 13 conductive. As transistor 13 becomes conductive, and transistor 12 becomes nonconductive, a current flows from the gate of transistor 22 through transistor 13 and through resistor 14. The current causes a voltage drop to occur between resistor 14 and V.sub.SS, and this voltage drop decreases the gate-to-source voltage on transistor 13. The decreased gate-to-source voltage on transistor 13 momentarily keeps the transistor in a saturation region, in which the current through the transistor is proportional to the gate-to-source voltage. This phenomenon slows the rate at which transistor 22 becomes nonconductive, reducing di/dt.
Also, D2 switches to a logic low and ultimately makes transistor 16 conductive and transistor 17 nonconductive. Resistor 15 similarly reduces the gate-to-source voltage on transistor 16 while current is flowing. Resistor 15 momentarily keeps transistor 16 in the saturation region, and keeps transistor 24 from becoming conductive as quickly as if no resistors were present.
In a typical embodiment, the integrated circuit is required to operate with a voltage on V.sub.DD between 4.5 volts and 5.5 volts while V.sub.SS is 0 volts, an input low voltage, VIL, at a maximum of 0.8 volts, and an input high voltage, VIH, at a minimum of 2.2 volts. An Ldi/dt voltage drop will be reflected on internal V.sub.DD and V.sub.SS terminals during switching, causing these voltages to depart from their external values and thresholds of input stage transistors to change. If the Ldi/dt voltage drop approaches VIH minus an internal switch level for Ldi/dt on V.sub.SS, or V.sub.DD minus VIL minus the internal switch level for Ldi/dt on V.sub.DD, a corresponding transistor on an input signal may fail to switch and to recogize the input signal in a particular state. Alternatively, if an input signal has assumed a steady-state value, an Ldi/dt voltage drop may cause the input transistor to switch incorrectly as if the input were chaning state. A smaller Ldi/dt voltage drop on V.sub.SS is necessary to cause an incorrect result than on V.sub.DD. Thus, switching to a logic low presents the worst case condition for di/dt. Whenever either a logic high input or a logic low input fails to be recognized, the whole circuit malfunctions.
While output buffer 35 provides a way to avoid integrated circuit malfunctions by using resistors 11, 14, 15, and 18 to reduce di/dt, it also suffers a disadvantage, especially in circuits in which speed is critical. When V.sub.DD decreases, a delay, from receiving D1 and D2 until the output signal is valid, increases. Since a worst case condition for speed of the remainder of the internal circuitry of the chip occurs at lowest V.sub.DD, 4.5 volts, the increased delay of the output buffer worsens the overall worst case delay of the chip.